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> Chapter 14 - Hardware Acceleration > FortiGate NP6 architectures > FortiGate-500E and 501E fast path architecture

FortiGate-500E and 501E fast path architecture

The FortiGate-500E and 501E each include one NP6 processor. All front panel data interfaces (port1 to 212, S1, S2, VW1, VW2, X1 and X2) connect to the NP6 processor. So all supported traffic passing between any two data interfaces can be offloaded.

The following diagram also shows the QSGMII and XAUI port connections between the NP6 processor and the front panel interfaces.

You can use the following get command to display the FortiGate-500E or 501E NP6 configuration. You can also use the diagnose npu np6 port-list command to display this information.

get hardware npu np6 port-list 
Chip   XAUI Ports        Max  Cross-chip 
                        Speed offloading 
------ ---- -------     ----- ---------- 
np6_0   0   x1           10G  Yes 
        1   port1        1G   Yes 
        1   port2        1G   Yes 
        1   port3        1G   Yes 
        1   port4        1G   Yes 
        1   port5        1G   Yes 
        1   port6        1G   Yes 
        1   port7        1G   Yes 
        1   port8        1G   Yes 
        1   port9        1G   Yes 
        1   port10       1G   Yes 
        1   port11       1G   Yes 
        1   port12       1G   Yes 
        1   s1           1G   Yes
        1   s2           1G   Yes 
        1   vw1          1G   Yes 
        1   vw2          1G   Yes 
        2   x2           10G  Yes 
------ ---- ------- ----- ----------